1. Field
The embodiments discussed herein relate to a successive approximation register analog-to-digital (AD) converter.
2. Description of Related Art
A successive approximation register analog-to-digital (AD) converter includes a digital-to-analog converter (DAC), a comparator, and a DAC control circuit. The successive approximation register AD converter samples an input voltage during a sampling period, holds the sampled voltage, and successively compares the sampled voltage with voltages to be compared during a comparison period that follows the sampling period. A plurality of voltages to be compared are generated in certain increments, i.e., ½ Vref, ¼ Vref, ⅛ Vref, . . . , in accordance with digital codes from the DAC control circuit. Vref may be a reference voltage. The comparator compares the voltages to be compared, which correspond to the digital codes, with the sampled voltage. The DAC control circuit changes a digital code in accordance with the comparison results of the comparator. A comparison operation is performed successively N times with the value of a voltage to be compared changing from a large value to a small value. An N-bit digital code corresponding to the sampled voltage is determined by the N-times successive comparison operations.
A related art is disclosed in, for example, Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, and Sanroku Tsukamoto in “A 10b 50MS/s 820 μW SAR ADC with On-Chip Digital Calibration,” 2010 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 384-385.